As the semiconductor packaging technology advances, different forms of packaging have been developed for semiconductor devices. For the traditional semiconductor devices, a semiconductor component, such as an integrated circuit, is firstly installed on a package substrate or a lead frame, then it is electrically connected to the package substrate or the lead frame, followed by encapsulation. The BGA (ball grid array) technique, such as PBGA, EBGA, and FCBGA, is one of the most advanced semiconductor packaging techniques. It is characterized by the installation of semiconductor components on a package substrate, and the back of the package substrate is implanted with many solder balls arrayed in a grid by the method of self-alignment, so that the same unit area of a carrier board for the semiconductor component can admit more I/O connections to suffice the demand for high integration of a semiconductor chip; the solder balls allow the entire package unit to be soldered together and electrically connected to the external devices.
Additionally, in order to meet the requirements for the computing of highly efficient chips like a microprocessor, a chipset, and a graphic chip, functions of circuit boards with wiring, such as signal transmission, bandwidth improvement, and resistive control, have to be improved so as to develop a package with higher I/O connections. However, the circuit boards for packaging semiconductor chips are presently equipped with thin wiring and small openings to meet the developmental trend of miniaturization, multi-function, high speed, and high frequency. The critical dimensions, including line width, line space, and aspect ratio, in the current circuit board production has been reduced from traditional size of 100 μm to 30 μm. More efforts are still being invested in the development for the precision of even thinner circuit wiring.
To enhance the wiring precision required for the circuit boards of semiconductor chip packaging, the semiconductor industry has developed a build-up technique, by which the surface of the core circuit board is stacked with a succession of a plurality of dielectric layers and circuit layers, and conductive vias are formed in the dielectric layers to thereby electrically connect the upper and lower circuit layers; wherein the build-up process is crucial to the circuit density of a circuit board.
FIGS. 1A to 1H show a conventional method for fabricating a built-up circuit board. First of all, as shown in FIG. 1A, a core board comprising an insulating layer 100 and a thin metal layer 101, such as a resin coated copper (RCC), is provided, then a plurality of through holes 102 are formed in the core board. As shown in FIG. 1B, another metal layer 103 is formed on the surface of the core board and on the inner wall of the through holes 102 by a copper electroplating process. As shown in FIG. 1C, a conductive or non-conductive hole-plugging material 11 (such as insulating ink or conductive paste that contains copper) fills the remaining spaces left in through holes 102, so that plated through holes (PTH) 102a are formed for electrically connecting the metal layer 103 on the top and bottom surfaces of the insulating layer 100. As shown in FIG. 1D, a redundant portion of the hole-plugging material 11 is removed by a scrubbing process to keep the surface of the circuits in the core board even and flat. As shown in FIG. 1E, the copper foil on both sides of the insulating layer 100 and the metal layer 103 are patterned to fabricate a finished core circuit board 10 having an inner circuit layer 104 on both sides.
Subsequently, as shown in FIG. 1F, a dielectric layer 12 is formed on the inner circuit layer 104 on the upper and lower surfaces of the core circuit board 10; a plurality of openings 120 are formed in the dielectric layer 12 by laser ablation. Then, as shown in FIG. 1G, after a conductive layer 13 is formed on the surface of the dielectric layer 12 and the openings 120 by electroless plating, a patterned resistive layer 14 is formed on the conductive layer 13, so as to form a circuit layer 15. As shown in FIG. 1H, the patterned resistive layer 14 is removed and etching is carried out, thereby removing the conductive layer 13 underneath the patterned resistive layer 14. The above process is repeated to form dielectric layers and built-up circuit layers with a view to fabricating a circuit board having multiple circuit layers.
However, in the process described above, an insulating layer covered with thin metal layers is used as the core, and a core circuit board is formed subsequently by forming circuits on the core, followed by the build-up process performed on the core circuit board, so as to fabricate a multi-layer circuit board that meets the required electrical requirements. As a result, the thickness of the finished multi-layer circuit board cannot be reduced, which is unfavorable to the developmental trend of a miniaturized semiconductor package structure. If the thickness of the core is reduced to as thin as 60 μm or less, the production of the multi-layer circuit board will be seriously compromised, and the production yield of circuit boards will decrease significantly.
In addition, there are extra steps in the production of core circuit boards, such as the hole-plugging and the scrubbing, which increase the production cost. More importantly, it is necessary to form a plurality of PTHs in the core circuit board; the diameter of a typical through hole formed by drilling is approximately 100 μm or more, while the diameter of the conductive via (laser blind hole) is approximately 50 μm. By comparison, the process of PTHs makes it more difficult to form a structure with finer circuits.
Moreover, in the process of the multi-layer circuit board described above, it is necessary to fabricate a core circuit board prior to forming dielectric layers and circuit layers, which consequently complicates the production steps, prolongs the process, and increases the production cost.
As a result, the industry urgently needs a solution to providing a circuit board structure and a method for fabricating the same, so as to overcome the drawbacks of the prior art, such as increased thickness of circuit boards, low wiring density, low yield, complicated production steps, a lengthy process, and a high production cost.